1. Field of the Invention
The present invention relates to a high-speed bipolar-to-CMOS logic converter circuit. More particularly, the invention relates to a converter circuit that allows to connection of a circuit portion provided in bipolar logic with another circuit portion provided in CMOS logic.
2. Discussion of the Related Art
Many conventional integrated circuits, used for example in the field of digital communications, use digital signal processing at a high clock rate.
Usually, a typical approach for the construction of these circuits is to divide the digital section of the circuit into two parts: one is produced in bipolar technology (ECL) while the other is produced in CMOS technology. In many digital signal processing systems, also those operating at a very high clock rate, an important part of the system operates with modest clock signals and therefore can be implemented by using CMOS techniques with results which are adequate for the requirements.
The possibility to implement the processing circuit by means of the two above-described technologies allows meeting the requirement of having increasingly high integration levels and bit rates; being able to meet this requirement is otherwise limited by the power consumption of bipolar circuits.
Two main drawbacks arise from the connection of bipolar digital circuits to digital circuits executed in CMOS technology, i.e., ECL logic circuits with CMOS logic circuits.
First, ECL logic states are not compatible with CMOS logic states; second, due to the need for temperature stability, the reference ground of a bipolar circuit is usually different from that of a CMOS circuit, as shown in FIG. 1, which illustrates a typical architecture of a bipolar and CMOS digital system.
In this figure, a main power supply line V.sub.cc1 supplies a voltage regulator 1, which supplies a voltage (i.e., V.sub.cc1 -V.sub.EE) which is temperature-stable for the bipolar circuit 2. Likewise, a voltage regulator 3 supplies a stable voltage V.sub.cc2 to the CMOS circuit 4. In order to correctly interconnect the bipolar circuit 2 and the CMOS circuit 4 it is necessary to have a circuit for converting from bipolar logic to CMOS logic, designated by the reference numeral 5.
In many cases, the voltage V.sub.cc1 is not regulated and varies by several hundred millivolts or by even more than one volt. In this case, it is necessary to provide a dynamic level shifting circuit in order to compensate for this variation. This increases the criticality and difficulty of the design of the converter circuit 5 used as interface between the bipolar digital portion and the CMOS digital portion of the system.
FIG. 2 illustrates a circuit solution commonly used for a bipolar-to-CMOS logic converter circuit.
This figure illustrates a switched current source, which is implemented by two bipolar transistors of the NPN type, designated by the reference numerals 6 and 7 and being coupled-emitter connected, and by two bipolar transistors of the PNP type, being current-mirror connected. This circuit inherently provides the required level shifter. However, the above-proposed circuit solution is affected by the fact that PNP transistors have poor performance; in particular, the PNP transistors used in circuits for radiofrequency applications are transistors of the lateral type with a very low cutoff frequency (f.sub.t &lt;100 MHz).
Since the output current in the circuit of FIG. 2 is switched by the PNP transistors 8 and 9, the maximum speed of the circuit cannot exceed a few megahertz.
A second conventional circuit solution is illustrated in FIG. 3 and again a coupled-emitter stage (with transistors 6 and 7 of the NPN type, similar to those of FIG. 1) is used but a fixed level shifter 10 is introduced. In this case, the drawbacks are due to the fact that there is a limited control of the driving current of the base of the output transistor 11 due to the variation in the voltage V.sub.cc1 and to the saturation of the transistor 11 when the output OUT is in the low state. These drawbacks lead to high power consumption and to a low operating frequency.